Topics
4. High Performance Architectures and Compilers
Description
This topic deals with architecture design and compilation for high performance systems. The areas of interest range from microprocessors to large-scale parallel machines; from general-purpose platforms to specialized hardware (e.g., graphic coprocessors, low-power embedded systems); and from hardware design to compiler technology. On the compilation side, topics of interest include programmer productivity issues, concurrent and/or sequential language aspects, program analysis, transformation, automatic discovery and/or management of parallelism at all levels, and the interaction between the compiler and the rest of the system. On the architecture side, the scope spans system architectures, processor micro-architecture, memory hierarchy, and multi-threading, and the impact of emerging trends.
Focus
Topics include but are not limited to:
- Compiling for multithreaded/multi-core and heterogeneous processors/architectures
- Compiling for emerging architectures (low-power embedded systems, reconfigurable hardware, processors in memory, graphics coprocessors)
- Iterative, just-in-time, feedback-oriented, dynamic, and machine learning-based compilation
- Static analysis and interaction between static and dynamic analysis
- Programmer productivity tools and analysis for high-performance architectures
- Program transformation systems
- Interaction between compiler, runtime system, hardware, and operating system
- Parallel computer architecture design - ILP, multi-threaded, and multi-core processors
- Power-performance efficient designs
- Software and hardware fault-tolerance techniques in large-scale parallel machines
- Memory hierarchy
- Application-specific, reconfigurable and embedded parallel systems
Topic committee
Global chair | ||
Pedro Diniz | INESC-ID | Portugal |
Vice chair | ||
Alain Darte | CNRS-Lyon | France |
Wolfgang Karl | University of Karlsuhe | Germany |
Local chair | ||
Ben Juurlink | Delft University of Technology | Netherlands |